AMD To Disclose Details on Carrizo APU At ISSCC 2015 – Features 28nm Excavator Core Architecture With 3.1 Billion Transistors

AMD is currently working on their next generation Carrizo APU which is coming this year to notebooks in the form of Carrizo-L while the desktop chips are planned for launched in early 2015. According to a report by EE Times, AMD will be disclosing details and technical information on Carrizo APU at the ISSCC 2015 (International Solid-State Circuits Conference).

AMD Carrizo APU To Feature 28nm Excavator Cores With A Die Size of 244.62 mm²

The ISSCC 2015 conference kicks on in February 2015 but the source has tipped off some details of the APU such as the die size, total number of transistors and data regarding efficiency of the new chip. The details say that AMD's Carrizo APU will feature the 28nm based x86 Excavator core architecture in dual and quad SKUs, best suited for Carrizo-L which is targeted at mainstream notebooks. The 28nm Carrizo APU will measure at 244.62 mm2 and pack 3.1 Billion transistors. For comparison, AMD's Kaveri APU packed 2.41 Billion transistors on a 245 mm2 die and was based on a 28nmSHP process from GlobalFoundries. The increased number of the total transistors could be due to two things, the new Excavator architecture and the use of new GCN graphics technology on Carrizo. Before we go into details, do read the following note:

AMD will disclose Carrizo, an integrated processor with its latest x86 core. The 28 nm chip measures 244.62 mm² and packs more than 3.1 billion transistors. Its new Excavator core is 23% smaller and uses 40% less power than AMD’s previous x86 core. via EETimes

Details we already know about Carrizo are that the APU would become the fifth installment in the Accelerated Processing Units family which will feature the latest Excavator core architecture. Powering the CPU side, these new x86 Excavator modular cores will leverage the IPC for greater performance compared to Steamroller. The mobile platform will feature both Quad Core and Dual Core variants but right now, we are looking at a glimpse of the top-end variant which shares 2 MB L2 cache. According to the official statement, the Excavator core will be 23% smaller and consume 40% lesser power than Kaveri APU. With the CPU die being small, it will give AMD more room to increase the GCN GPU die on the APU.

Prior to this leak, rumors revealed that Carrizo will feature 30% performance increase over Kaveri generation of processors which we thought was pure speculation at best but the slide clearly mentions a 30% increase at only 15W power input which is pretty impressive. Additionally, AMD will also add AVX2, BMI2, MOVBE and RDRAND support to the instruction set which brings the extension feature set close to Intel’s Haswell. Since the targeted platforms for these APUs are notebooks, all-in-ones and convertibles, they will be shipped in BGA )FP4) package and will ship in variants ranging in TDPs of 12/15/35W. The desktop variants will be rated at a power draw of 40/45/65W.

On the GPU side, we have the 3rd Generation GCN (Volcanic Islands) core which is a great plus point for this level of APU. You should keep in mind that the Volcanic Islands graphics isn’t the codename for AMD’s Radeon R200 lineup but infact used to denote their flagship Hawaii based chips. The integrated graphics would still be based on the 28nm process and its hard to say whether the Compute Unit count will increase in the Carrizo APU generation of products. We will definitely see an improved and efficient design which will allow faster clock speeds on these great integrated chips which make many upcoming games run off without the need of a discrete graphics card at decent detail quality.

The graphics die will still feature 8 Compute Units which denote 512 stream processors along with higher memory efficiency which will deliver better performance throughput since APUs are generally bandwidth starved, Delta color compression and feature full HSA support with a high-performance integrated bus for graphics and DRAM along side some software enhancements such as Fine-grain preemption for context switches and in addition to Mantle, feature support for DirectX 12 API too. It remains to be seen if the faster desktop variants will get an updated die since reports have alleged that features from Tonga will be derived in the latest installment of  APUs. This could mean several things, the features on Tonga such as color compression and memory bandwidth optimizations could be in place along with better XDMA Dual graphics support plus the addition of more stream processors and GCN Compute units.

The most interesting thing about Carrizo, aside from its technical specifications is also the design of the chip itself. AMD for the first time is aiming for a true SOC design eliminating the need of a separate FCH as was the case with Kaveri mobile which requires Bolton FCH for additional connectivity options. The FCH will be integrated on the die itself which will deliver Security, Display, Audio, PCI-e, SATA, SD, USB, Multimedia, UART/12C. CLCKGen and Misc I/O connectivity. AMD is aiming for UVD6, VCE3 and a audio co-processors with H.264 encode while feature a display control engine “DCE11″. With HDMI 2.0 that provides up to 3 display interfaces and PCI-e Gen 3.0 x8 for discrete GPU expansion and PCI-e 3.0 x4 for GPP, the APU begins to look like a decent improvement over Kaveri from a design perspective.  The FCH can deliver 4 USB 3.0 / 2.0 ports, 4 USB 2.0 ports and 2 SATA 3 ports while the memory controller allow for Dual Channel DDR3 memory rated at 2133 MHz in SoDIMM form factor (One per channel).

While Carrizo-L is the first to hit the market in 2014, the actual Carrizo APU will hit next year in 2015 which will feature both mobile and desktop platforms. The mobile platform is targeted as a SOC while desktop chips will be compatible with FM2+ socket with the A88X “Bolton” FCH. Some early specifications have been leaked which we have detailed in an article here.

MD Carrizo APU (Mobile/Desktop) Comparison Chart:

 AMD Kaveri APU Technical Specifications: